VLSI Backend Engineer - Library Characterization

Yokneam · Full-time · Senior

About The Position

Chain Reaction designs and builds hardware that fuels disruptive blockchain technologies by accelerating compute performance. Our world class teams are transforming the future of data, creating the infrastructure that will power the next generation of secure, scalable, green computing. The main bottleneck in scaling cutting edge solutions in privacy tech, data-analysis and real-time computing is acceleration – existing hardware cannot keep up with data processing needs. Chain Reaction’s products reshape how data is processed and used on a global scale, and we’re looking for the brightest people to join us.

 We are looking for talented and ambitious individuals to join our Yoqneam IC team.


The candidate will be responsible for the characterization of standard cell and custom cell libraries and for generating the latest library formats with cutting edge tools and methodologies.  

Work in interdisciplinary teams and help develop timing/power/noise libraries for standard cells and custom cells at voltage ranges down to near-threshold in latest statistical library formats.

Help to ensure the “First Time Right” of our IC Designs by ensuring high quality library deliverables.

Understand design requirements, block level specifications and circuit documentation and perform library characterization in accordance. For this, the candidate will collaborate closely with the analog and digital teams.

Assume responsibility for continuously improving our library characterization methodology.

Work closely with EDA vendors on latest tool feature development and qualification.



  •  BSc or MSc in Electrical Engineering or Computer Engineering 
  •  4+ years of relevant experience.
  • High expertise in library characterization including LVF libraries. Familiar with Liberty models and their application to digital implementation and signoff flows.
  • Hands-on experience running SPICE simulation and understanding spice decks.
  • Experience with 16nm technologies or more advanced.
  • Experience with Cadence Liberate or Synopsys Prime-Lib
  • Experience with STA tools with Synopsys Primetime and/or Cadence Tempus
  •  Strong independent and motivated to learn quickly, hard-working, and is results oriented.


  • Experience with Synthesis/PnR EDA tools is a big advantage.
  • Strong proficiency in scripting language, such as, Perl, Tcl, Python, Make, and automation methods/algorithms.

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